In recent years, digital still cameras and digital video cameras with over one million pixels have become widely used. These digital still cameras use a plurality of CCD image sensors, an area sensor having CMOS image sensors, and an A/D converter, and digitally convert output signals (analog image signals) of the area sensor by the A/D converter, to obtain digital image data. Further, since digital still cameras in recent years require an A/D conversion speed of about 20 MHz, flash type A/D converters, serial-parallel type A/D converters, pipeline type A/D converters and the like, which can perform A/D conversions at high speeds, are often used.
FIG. 15 shows an example of a conventional circuit (digital image photographing circuit) that images digital pictures. As shown in FIG. 15, the digital image photographing circuit 80 is equipped with an area sensor 81, a CDS circuit 84, and a pipeline type A/D converter 85. Also, the area sensor 81 includes a sensor section 82 and a data accumulation section 83, wherein the sensor section 82 includes image sensors disposed in a matrix configuration.
The image sensors within the sensor section 82 output analog image signals according to the amount of received light to the data accumulation section 83. More specifically, each of the image sensors in the sensor section 82 outputs (Vb) V when it receives the minimum amount of light within the range of its light sensing capability, outputs (Vt) V when it receives the maximum amount of light within the range of its light sensing capability, and linearly outputs a potential between (Vb) V and (Vt) V according to the amount of light received when it receives an amount of light between the two. It is noted that the potential difference between (Vb) V and (Vt) V is about 0.6˜0.8 V.
The data accumulation section 83 amplifies the analog image signal received from the sensor section 82 with a predetermined amplification, records the same as a signal having an amplitude ranging between (VB) V and (VT) V, and serially outputs the same to the CDS circuit 84. It is noted that the potential difference between (VB) V and (VT) V is about 2 V.
The CDS circuit 8 removes noise components from the analog image signals serially output from the data accumulation section 83, and serially outputs the same to the A/D converter 85.
The A/D converter 85 receives the analog image signal from the CDS circuit 84, and outputs an unsigned integer value having a width of 10 bits (digital image data). More specifically, the A/D converter 85 outputs zero (0) when it receives an analog image signal at (VB) V, outputs 1023 when it receives an analog image signal at (VT) V, and linearly outputs a value between 0 and 1023 according to a potential received when the received potential is between the two.
FIG. 16 is a graph showing the relation (A/D conversion characteristic) between analog image signals received and digital image data output by the A/D converter 85. In FIG. 16, values of analog image signals received by the A/D converter 85 are indicated along a transverse axis, and values of digital image data output by the A/D converter 85 along a vertical axis.
In general, a digital image data accuracy to at least about 10 bits to 12 bits is required to secure the gradation of an image, and therefore the width of a bus that connects an output of the A/D converter 85 and an image processing circuit in a succeeding stage needs to be broadened, and a large capacity image memory is required to record digital image data.
Also, there is a trend to increase the number of pixels in area sensors, and therefore faster A/D converters (about 20 MHz˜50 MHz) are in demand for taking in the entire image in a shorter time. As a result, pipeline type A/D converters that take in images at high speeds are required. However, although a pipeline type A/D converter with multiple bits is fast and highly accurate, it is a large circuit, expensive and consumes a lot of power. Also, securing the accuracy of a multiple-bit circuit may be problematic. For these reasons, column type A/D converters, which have a smaller circuit and require a lower power consumption than flash type A/D converters, serial-parallel type A/D converters or pipeline type A/D converters, are also used. FIG. 17 shows an example of a semiconductor device using a column type A/D converter. As indicated in FIG. 17, the semiconductor device 90 is equipped with an area sensor 91 having image sensors disposed in a matrix configuration, and a column type A/D converter 92 that receives analog image signals from the area sensor 91 and outputs digital image data of 10-bit width.
When the column type A/D converter is used, as indicated in FIG. 17, the area sensor and the column type A/D converter can be integrated into a single semiconductor device. However, in order to achieve a highly accurate A/D conversion with a column type A/D converter, the cycle of sweep signals in ramps needs to be made longer, which is problematic because A/D conversion takes a long time.
To reduce the memory capacity necessary for the digital expression of a picture, Japanese laid-open patent publication (Tokkai) Hei 8-294086 (hereafter also referred to as “Reference 1”) describes a compression method that compresses a digital input expression in first predetermined bits representing a picture in a digital output expression in second predetermined bits representing the picture. The compression method includes the steps of: (a) determining a logarithmic function for converting a digital input in first predetermined bits into a digital output in second predetermined bits; (b) replacing a part of the logarithmic function with a polynomial function; and (c) compressing the digital input in first predetermined bits into the digital output in second predetermined bits through a processor by using the logarithmic function and the polynomial function to thereby reduce the memory capacity necessary for storing the picture.
However, although the compression method described in Reference 1 can reduce the memory capacity for storing pictures, it needs a much higher accuracy in its A/D converter, and also needs a circuit that includes a large capacity memory called a look-up table. Also, in the compression method described in Reference 1, because a part of the logarithmic function is replaced with a polynomial function, a knee characteristic cannot be realized.
Also, Tokkai Hei 7-162886 (hereafter also referred to as “Reference 2”) describes a method for performing a film-like compression on a video signal. The video signal film-like compression method includes the steps of: (a) supplying a video signal to a compression means; and (b) film-like compressing the video signal within the compression means in accordance with a film-like compression function and generating a compressed video signal from the video signal.
However, the video signal film-like compression method described in Reference 2 processes a video signal in a manner to incorporate a film-like compression characteristic into the video signal, and does not narrow the bit width of a digital image or the bus width, or realize a knee characteristic.
In view of the problems described above, it is a first object of the present invention to provide an image signal processing circuit that can narrow the bus width of a bus that outputs digital image data, realize a knee characteristic, record digital image data having a great dynamic range with a small memory, and realize a lower power consumption with a simple and low cost circuit while reserving a dynamic range and accuracy necessary for image data. Furthermore, it is a second object of the present invention to provide a semiconductor device that includes such an image signal processing circuit.